Thursday, October 31, 2013

A simple cache simulator project

Cache simulator fun — CodeChat template version 0.0 documentation

Cache simulator fun

The task in this homework is to write a simple cache simulator. Your program has the following requirements.

Input File Format

Your program must be able to parse memory trace files that are in the Dinero text format (Dinero is a well‐known cache simulator). This is a simple text format that is given below:
2 20d  Dinero input format "din" is an ASCII file with
2 211  one LABEL and one ADDRESS per line. The rest of
0 1fc780  the line is ignored so that it can be used for
1 7fffccb0  comments.
2 213
2 217  LABEL = 0  read data
0 1fc77c   1  write data
1 7fffccac   2  instruction fetch
2 219   3  escape record (treated as unknown access type)
2 21d   4  escape record (causes cache flush)
0 1fc778
1 7fffcca8  0 <= ADDRESS <= ffffffff where the hexadecimal addresses
2 21f  are NOT preceded by "0x."
2 223
2 220
You will be provided with a couple of memory trace files in this format along with ‘golden’ results from several sample runs. In the above format, ‘read data’ and ‘instruction fetch’ both count as ‘read accesses’. You are to simulate a unified cache, which means instruction and data are both stored in the same cache.

Program Options, Program output

You program must be able to be run from the command line and support the following command line format:
Program_name infile <options>
Valid options are:
<-l1-usize num_bytes> : total size in bytes
<-l1-ubsize num_bytes> : block size in bytes
<-l1-uassoc num_levels> : associativity level
<-l1-urepl type> : replacement policy, 'l' - LRU, 'f' - FIFO
<-l1-uwalloc type> : write allocation policy, 'a' - always, 'n'-never
These options are compatible with the DineroIV cache simulator. Sample command line runs are shown below (the program name is cache_sim, and the input file is tex.din):
cache_sim tex.din -l1-usize 1024 -l1-ubsize 32 -l1-uassoc 32 -l1-urepl f -l1-uwalloc n
cache_sim tex.din -l1-usize 1024 -l1-ubsize 32 -l1-uassoc 4 -l1-urepl l -l1-uwalloc a
cache_sim tex.din -l1-usize 1024 -l1-ubsize 32 -l1-uassoc 1 -l1-urepl l -l1-uwalloc a
Your program must output the number of cache misses for the given options and input file. Sample output is shown below. The only important information in the output is the line ‘Demand Misses 42825’ – your output must contain a line like this, in this exact format as my regression script parses the output and looks for a line that starts with ‘Demand Misses’
cache_sim tex.din -l1-usize 1024 -l1-ubsize 32 -l1-uassoc 4 -l1-urepl l -l1-uwalloc a
Running with l1-usize=1024, l1-ubsize=32, l1-assoc=4, l1-repl=l, l1-uwalloc=a
Number of cache lines is: 8
Demand Accesses 832477
Demand Misses 42825

What you are provided

The ZIP archive for this homework contains the following:
  • traces/ folder – contains three trace files that can be used for testing.
  • cache_sim.exe - Windows x86 executable that is my solution to this problem. This can be used to obtain sample results
  • goldAll_espresso.log, goldAll_tex.log - correct output for several runs using the trace files espresso.din, tex.din. Dr. Reese reserve the right to test your program with more than these options.
  • cache_sim.py - Skeleton files that have parsing of the required command line arguments in Python. You can use these as starting points if you desire.
  • regress.check.py - A regression test script that takes three arguments: the name of a golden cache simulation executable (i.e., ‘cache_sim.exe’), the name of your cache simulation executable, and the name of a trace file. It will run both programs on the trace file using several options, compare the results, and report failures.

Implementation

Skipped

Indices and tables

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